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An Arithmetic Structure for Test Data Horizontal Compression

Abstract : We propose a method for reducing test data volume of integrated circuits or cores in a System-on-Chip. This method is intended to reduce the required number of Automatic Test Equipment (ATE) output channels compared to the number of scan-in input pins in a classical multi-chain implementation (horizontal compression). Compression and decompression are based on arithmetic operations and structures which present a very low area overhead. The proposed compression scheme does not impact the fault coverage achieved by the original test sequence before compression.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108837
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Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. An Arithmetic Structure for Test Data Horizontal Compression. DATE: Design, Automation and Test in Europe, Feb 2004, Paris, France. pp.428-434, ⟨10.1109/DATE.2004.1268884⟩. ⟨lirmm-00108837⟩

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