With increasing clock frequencies and shrinking process geometries, both capacitive and inductive crosstalks become important concerns in designs. In deep sub-micron technologies, we can ignore neither the amplitude of the noise due to the coupling between bus lines, nor the delay variation due to this crosstalk voltage. In this paper we study different design solutions on bus configurations in order to take advantage of DSM technologies, and evaluate their impact on crosstalk reduction. The use of intra-layer low-k dielectrics reduces the coupling capacitances and a permittivity of two reduces the crosstalk voltage by 22%. An electrical screening ground lines solution between signal lines exhibits favourable interest for a typical SoC structure. Space between lines can be significantly reduced for an equivalent crosstalk voltage. Crosstalk and timing performances of these different solutions are evaluated and then compared. The reduction of the input switching delay with technology evolution leads to an important increase in the inductive effect. These lines are modelled as RC and RLC lines, and the two models are compared to define the effects caused by neglecting inductance.