Optimizing digital designs implies a selection of circuit implementation based on different cost criteria. Post-processing methods such as transistor sizing, buffer insertion or logic transformation can be used for optimizing critical paths to satisfy timing constraints. However most optimization tools are not able to select between the different optimization alternatives and have high CPU execution time. In this paper, we propose an optimization protocol based on metrics allowing to characterize a path and to select the best optimization alternative. We define a way to characterize the design space of any circuit implementation. Then we propose a constraint distribution method allowing constraint satisfaction at nearly minimum area. This quasi optimal tool is implemented in an optimization tool (POPS) and validated by comparing the area necessary to satisfy delay constraints applied to various benchmarks (ISCAS’85) to that resulting from an industrial tool.