Definition of P/N Width Ratio for CMOS Standard Cell Library

Abstract : The efficiency of cell-based design synthesis of high performance circuit is strongly dependent on the content of the library. Great effort has been given in the design of libraries, to define the optimal selection of the logic gate drive strength. But few justifications are available to determine the P/N width ratio of each cell. In this paper we use an extension of the logical effort model to characterize the dissymmetry of gate delay and define the best P/N width ratio allowing a path minimum area implementation under delay constraint. This delay model explicitly represents the sensitivity of delay to gate structure and P/N width ratio. Application is given on a 0.18µm process on different logic path implementations.
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Communication dans un congrès
DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.769-773, 2004
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Contributeur : Christine Carvalho de Matos <>
Soumis le : samedi 21 janvier 2017 - 20:16:04
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
Document(s) archivé(s) le : samedi 22 avril 2017 - 13:07:09

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  • HAL Id : lirmm-00108933, version 1

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Alexandre Verle, Philippe Maurine, Nadine Azemard, Daniel Auvergne. Definition of P/N Width Ratio for CMOS Standard Cell Library. DCIS: Design of Circuits and Integrated Systems, Nov 2004, Bordeaux, France. 19th International Conference on Design of Circuits and Integrated Systems, pp.769-773, 2004. 〈lirmm-00108933〉

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