Among the attacks applied on secure circuits which are described in the literature, we can find fault injection techniques. Fault attacks are conduced using a combination of environmental conditions that cause the chip to produce computational errors that can leak protected information. The aim of this article is to attempt to build a pertinent fault model representing CMOS circuit behaviour in presence of short supply voltage variations. The behaviour of the circuit in presence of fault depends strongly on the basic gates (combinational logic, registers...) architecture. Therefore, the fault model depends on the sensitivity of these basic elements towards the faults generated by the supply voltage glitches.