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Circuit Performance Optimization under Delay Constraints

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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00117119
Contributor : Martine Peridier <>
Submitted on : Thursday, November 30, 2006 - 10:20:34 AM
Last modification on : Thursday, September 12, 2019 - 9:23:48 PM

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  • HAL Id : lirmm-00117119, version 1

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Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Circuit Performance Optimization under Delay Constraints. DCIS: Design of Circuits and Integrated Systems, Nov 2006, Barcelona, Spain. ⟨lirmm-00117119⟩

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