In this paper, the use of piezoresistive CMOS beams is addressed with a particular focus on offset and noise rejection problems in a Wheatstone bridge. Using a test-chip (a magnetometer), the mismatch between resistors (on the substrate) and gauges (suspended) is experimentally studied. Both thermal and mechanical causes are analyzed and modelled. As a result, it appears that 80% of the offset has thermal origin and is predictable during the design. Other contributors are residual stress resulting from the MEMS releasing process and standard CMOS spreading. Statistical study on about 60 samples tends to demonstrate that uncertainties on the offset only depend on CMOS scatterings. Because mismatch in the Wheatstone bridge causes both offset and poor PSRR, it is necessary to overcome this problem. Two mismatch cancellation techniques are finally reported. The first one is based on the use of a dummy structure that embeds the reference resistor. The second one implements a feedback circuitry to balance the Wheatstone bridge through its biasing.