Asynchronous CMOS data dependent adders are introduced in this paper. The proposed architectures result from modifications of classical structures of addition. These modifications, although simple, allow a significant reduction of the average latency of these operators without modifying the datapaths nor degrading the area requirement. In order to validate the suggested architecture, operators have been designed with a standard CMOS technology (0.35μm) for various timing constraints. The design spaces obtained have thereafter been compared to their synchronous counterparts.