A secure Scan Design Methodology

David Hély 1 Frédéric Bancel 1 Marie-Lise Flottes 2 Bruno Rouzeyre 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presented in the literature in order to securize the scan chain. Nevertheless, the different proposed techniques are all ad hoc techniques, which are not always easy to integrate into a completely automated design flow or in an IP reuse environment. In this paper, we propose a scan chain integrity detection mechanism, which respects both automated design flow and IP reuse environment.
Type de document :
Communication dans un congrès
DATE: Design, Automation and Test in Europe, Mar 2006, Munich, Germany. IEEE, Proceedings of the Design Automation & Test in Europe Conference, pp.1177-1178, 2006, 〈10.1109/DATE.2006.244019〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00132516
Contributeur : Christine Carvalho de Matos <>
Soumis le : mercredi 21 février 2007 - 17:13:07
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. A secure Scan Design Methodology. DATE: Design, Automation and Test in Europe, Mar 2006, Munich, Germany. IEEE, Proceedings of the Design Automation & Test in Europe Conference, pp.1177-1178, 2006, 〈10.1109/DATE.2006.244019〉. 〈lirmm-00132516〉

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