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HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded Systems

Nicolas Saint-Jean 1 Gilles Sassatelli 2 Pascal Benoit 2 Lionel Torres 2 Michel Robert 2
1 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. Our architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and an asynchronous network on chip. S-Scale is a multi-threaded sequential programming model with dedicated communication primitives handled at run-time by a simple Operating System we developed. The hardware validations and experiments on applications such as MJPEG and FIR filters demonstrate the scalability of our approach and draws interesting perspectives for distributed strategies of task control management.
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00154074
Contributor : Martine Peridier <>
Submitted on : Tuesday, June 12, 2007 - 4:18:39 PM
Last modification on : Tuesday, June 26, 2018 - 1:18:34 AM

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  • HAL Id : lirmm-00154074, version 1

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

Citation

Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded Systems. ISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, pp.21-28. ⟨lirmm-00154074⟩

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