HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded Systems

Abstract : Scalability of architecture, programming model and task control management will be a major challenge for MP-SOC designs in the coming years. The contribution presented in this paper is HS-Scale, a hardware/software framework to study, define and experiment scalable solutions for next generation MP-SOC. Our architecture, H-Scale, is a homogeneous MP-SOC based on RISC processors, distributed memories and an asynchronous network on chip. S-Scale is a multi-threaded sequential programming model with dedicated communication primitives handled at run-time by a simple Operating System we developed. The hardware validations and experiments on applications such as MJPEG and FIR filters demonstrate the scalability of our approach and draws interesting perspectives for distributed strategies of task control management.
Type de document :
Communication dans un congrès
ISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, IEEE, pp.21-28, 2007, 〈http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.51〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00154074
Contributeur : Martine Peridier <>
Soumis le : mardi 12 juin 2007 - 16:18:39
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00154074, version 1

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Nicolas Saint-Jean, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Michel Robert. HS-Scale: A Hardware-Software Scalable MP-SOC Architecture for Embedded Systems. ISVLSI'07: IEEE Computer Society Annual Symposium on VLSI, 2007, Porto Allegre, Brazil, IEEE, pp.21-28, 2007, 〈http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.51〉. 〈lirmm-00154074〉

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