Test and Security

Abstract : As security remains a major concern in more and more application, security of internal IP with scan chain access is fast becoming a major concern in certain parts of the electronics industry. High quality end-production testing must complete Design For Security (DFS) techniques in order not to deliver supposedly secure chips that may fail due to process issues. However high testability and high security may lead to a difficult cohabitation and inserting testability features into a secure design cannot be performed using traditional approaches. In addition to the testability concerns, security weakness introduced by these new features must be taken into account. In this presentation, countermeasures in order to make Design For Testability compliant with security constraints are discussed.
Keywords : Testability Security
Type de document :
Communication dans un congrès
CryptArchi'07: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2007, Montpellier, France. 2007, 〈http://cryptarchi.univ-st-etienne.fr/workshop07/index.htm〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00163017
Contributeur : Marie-Lise Flottes <>
Soumis le : lundi 16 juillet 2007 - 15:52:21
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00163017, version 1

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Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre, Marion Doulcier. Test and Security. CryptArchi'07: Cryptographic Architectures Embedded in Reconfigurable Devices, Jun 2007, Montpellier, France. 2007, 〈http://cryptarchi.univ-st-etienne.fr/workshop07/index.htm〉. 〈lirmm-00163017〉

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