On-Line Self-Test of AES Hardware Implementations - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2007

On-Line Self-Test of AES Hardware Implementations

Abstract

In this paper we propose an on-line self-test architecture for hardware implementations of Advanced Encryption Standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. Because Substitution boxes (S-Box) represent the largest hardware in this architecture, we focus on faults affecting these S-Boxes and propose a trade-off between hardware overhead and fault latency. We show that our solution is very effective while keeping the area overhead very low. Moreover, this architecture does not weak the device with respect to side-channel attacks based on power analysis. On the contrary, it makes more difficult this type of attack.
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Dates and versions

lirmm-00163405 , version 1 (17-07-2007)

Identifiers

  • HAL Id : lirmm-00163405 , version 1

Cite

Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. On-Line Self-Test of AES Hardware Implementations. DSN'07: Workshop on Dependable and Secure Nanocomputing, Jun 2007, Edinburgh, United Kingdom. ⟨lirmm-00163405⟩
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