Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2007

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Abstract

In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings

Dates and versions

lirmm-00178525 , version 1 (11-10-2007)

Identifiers

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Benoit Lasbouygues, Robin M. Wilson, Nadine Azemard, Philippe Maurine. Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops. DATE: Design, Automation and Test in Europe, Mar 2007, Nice, France. ⟨10.1109/DATE.2007.364426⟩. ⟨lirmm-00178525⟩
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