Evaluation of Design for Reliability Techniques in Embedded Flash Memories

Abstract : Non-volatile Flash memories are becoming more and more popular in Systems-on-Chip (SoC). Embedded Flash (eFlash) memories are based on the well-known floatinggate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems ; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as Error Correction Code (ECC), Redundancy or Threshold Voltage (VT) Analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed.
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Communication dans un congrès
DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.1593-1598, 2007, 〈10.1109/DATE.2007.364529〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00179951
Contributeur : Martine Peridier <>
Soumis le : mardi 11 décembre 2007 - 14:53:20
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19
Document(s) archivé(s) le : dimanche 11 avril 2010 - 23:12:04

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Benoît Godard, Jean-Michel Daga, Lionel Torres, Gilles Sassatelli. Evaluation of Design for Reliability Techniques in Embedded Flash Memories. DATE: Design, Automation and Test in Europe, Apr 2007, Nice, France. pp.1593-1598, 2007, 〈10.1109/DATE.2007.364529〉. 〈lirmm-00179951〉

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