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Fully Digital Test Solution for a Set of ADCs and DACs embedded in a SiP or SoC

Vincent Kerzérho 1 Philippe Cauvet 2 Serge Bernard 1 Florence Azaïs 1 Mariane Comte 1 Michel Renovell 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : The trend towards highly integrated electronic devices leads to the growth of the System-in-Package (SiP) and System-on-Chip (SoC) technologies, where data converters play a major role in the interface between the real analogue world and the digital processing. Testing these converters with accuracy and at a low cost represents a big challenge, because the observability and controllability of these blocks is reduced and the test operation requires a lot of time and expensive analogue instruments. The purpose of this paper is to present a new Design-for-Test (DFT) technique called “Analogue Network of Converters”. This technique aims at testing a set of Analogue-to-Digital Converters (ADC) and Digital-to-Analogue Converters (DAC) in a fully digital setup (using a low cost digital tester). The proposed method relies on a novel processing of the harmonic distortion generated by the converters and requires an extremely simple additional circuitry and interconnects.
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Submitted on : Monday, December 10, 2007 - 10:45:30 AM
Last modification on : Wednesday, August 28, 2019 - 7:12:02 PM
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Vincent Kerzérho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, et al.. Fully Digital Test Solution for a Set of ADCs and DACs embedded in a SiP or SoC. IET Computers & Digital Techniques, Institution of Engineering and Technology, 2007, 1 (3), pp.146-153. ⟨lirmm-00195172⟩

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