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A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing

Abstract : High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.
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Submitted on : Tuesday, December 11, 2007 - 12:04:17 PM
Last modification on : Friday, August 5, 2022 - 10:48:00 AM
Long-term archiving on: : Monday, April 12, 2010 - 6:52:44 AM


  • HAL Id : lirmm-00195682, version 1



Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, et al.. A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing. ITC'07: International Test Conference, Oct 2007, pp.25.1. ⟨lirmm-00195682⟩



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