Post-Layout Timing Simulation of CMOS Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Year : 1993

Post-Layout Timing Simulation of CMOS Circuits

Abstract

As a necessary aid to system integration, the authors present the implementation and performance of a pattern-dependent timing simulator, PATH-RUNNER. Organized around an explicit formulation of delays, this is an event-driven simulator which processes only transitions with gates controlled by events. Extraction of conduction paths from a general decomposition of data paths in unidirectional blocks allows general conflictual situations to be solved. Configuration problems detected during the evaluation, such as pulse rejection and strength conflicts, are illustrated, and effective solutions of conflictual configurations are given. It is shown that the implementation of a two-pass algorithm results in a significant improvement of speed. Execution times have been found to be nearly linear with the node numbers. Comparison of simulation times obtained from other timing simulators is given. SPICE compatibilities of PATH-RUNNER allow automatic real characterization of data paths from post-layout extracted net lists, with SPICE-like accuracy for evaluation of delays on real structures.
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Dates and versions

lirmm-00239206 , version 1 (05-02-2008)

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Denis Deschacht, Michel Robert, Nadine Azemard, Daniel Auvergne. Post-Layout Timing Simulation of CMOS Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993, 12 (8), pp.1170-1177. ⟨10.1109/43.238609⟩. ⟨lirmm-00239206⟩
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