POPS: A tool for delay/power performance optimization

Nadine Azemard 1, * Daniel Auvergne 1
* Auteur correspondant
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Based on an incremental path search algorithm, this paper addresses the problem of performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from industrial tools on examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.
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Article dans une revue
Journal of Systems Architecture, Elsevier, 2001, 47 (3), pp.375-382. 〈10.1016/S1383-7621(00)00055-2〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239314
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 14:22:33
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18

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Nadine Azemard, Daniel Auvergne. POPS: A tool for delay/power performance optimization. Journal of Systems Architecture, Elsevier, 2001, 47 (3), pp.375-382. 〈10.1016/S1383-7621(00)00055-2〉. 〈lirmm-00239314〉

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