Transition Time Modeling in Deep Submicron CMOS

Abstract : As generally recognized, the performance of a CMOS gate, such as propagation delay time or short circuit power dissipation, is strongly affected by the nonzero input signal transition time. This paper presents an analytical model of the transition time of CMOS structures. The authors first develop the model for inverters, considering fast and slow input signal conditions, over a large design range of input-output coupling capacitance and capacitive load. They then extend this model to more complex gates. The validity of the presented model is demonstrated through a comparison with HSPICE simulations on a 0.18 /spl mu/m CMOS process.
Type de document :
Article dans une revue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352- 1363
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239324
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 14:39:03
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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  • HAL Id : lirmm-00239324, version 1

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Philippe Maurine, Mustapha Rezzoug, Nadine Azemard, Daniel Auvergne. Transition Time Modeling in Deep Submicron CMOS. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, 2002, 21 (11), pp.1352- 1363. 〈lirmm-00239324〉

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