Gate Sizing for Low Power Design

Abstract : Low power design based on minimal size gate implementation induces great speed penalty. We present a new gate sizing method for improving the speed performance of static logic paths designed in submicron CMOS technologies without increasing the power dissipation obtained with a minimal surface implantation. This methodology is based on the definition of local gate sizing criterion. It has been deduced from analytical models of the output transition time and of the short circuit power dissipation which are briefly introduced. Validations are given, on a 0.18 µm process using Hspice simulations(Bsim3v3 level69).
Type de document :
Chapitre d'ouvrage
SOC Design Methodologies, Kluwer Academic Publishers, pp.301-312, 2002
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239359
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 15:42:58
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00239359, version 1

Citation

Philippe Maurine, Nadine Azemard, Daniel Auvergne. Gate Sizing for Low Power Design. SOC Design Methodologies, Kluwer Academic Publishers, pp.301-312, 2002. 〈lirmm-00239359〉

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