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POPS: A tool for Delay/Power Performance/Optimization

Abstract : Based on an incremental path search algorithm, this paper addresses the problem of performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from industrial tools on examples of path enumeration and optimization evaluated on several ISCAS'85 benchmarks.
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Contributor : Nadine Azemard Connect in order to contact the contributor
Submitted on : Tuesday, February 5, 2008 - 5:05:29 PM
Last modification on : Friday, October 22, 2021 - 3:07:36 PM



Nadine Azemard, Michel Aline, Daniel Auvergne. POPS: A tool for Delay/Power Performance/Optimization. ASIC-SoC: International ASIC/SOC Conference, Sep 2000, Arlington, VA, United States. pp.276-280, ⟨10.1109/ASIC.2000.880715⟩. ⟨lirmm-00239434⟩



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