Defining the Maximum Speed of CMOS Gate Library

Abstract : The robust estimation of the maximum speed of combinatorial elements is of prime importance when comparing different library suppliers or predicting the performance improvement of new processes. Considering the input ramp effect and the input-to-output coupling capacitance, we propose in this paper, a new definition of both the inertial delay and the maximum speed that can be achieved with standard combinatorial gates. Validations are given on several processes ranging from 0.8µm to 0.18µm.
Type de document :
Communication dans un congrès
DCIS'02: XVII Design of Circuits and Integrated Systems Conference, Nov 2002, Santander, Espagne, pp.81-86, 2002
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239455
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 17:47:09
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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  • HAL Id : lirmm-00239455, version 1

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Philippe Maurine, Nadine Azemard, Daniel Auvergne. Defining the Maximum Speed of CMOS Gate Library. DCIS'02: XVII Design of Circuits and Integrated Systems Conference, Nov 2002, Santander, Espagne, pp.81-86, 2002. 〈lirmm-00239455〉

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