The design of high performance circuits requires trade-off between speed, power and area. Based on a reasonable modeling of delay, this work presents a method to define metrics allowing to characterize the criticality of nodes. The purpose of this work is to define indicators for the selection of fanout optimization alternatives. The validation of the determination of these indicators is obtained through comparison with limit of loads determined from Spice simulations. The application to various ISCAS benchmarks shows that, without enumeration, an initial path delay improvement can be obtained at reduced area/power cost.