Continuous Representation of the Performance of a CMOS Library

Abstract : In a standard industrial approach the timing performance verification is obtained using a tabular method that necessitates a great amount of simulations. They must specify, for each drive in each logic family: the load, the input slope, the temperature and the supply voltage sensitivity, for each edge, of the transition time and propagation delay. Extending a logical effort like based model of timing performance of CMOS structures we show in this paper that it is possible to define a specific performance representation allowing a continuous representation of the performance sensitivity of a complete family. We describe the parameter calibration procedure and validate the proposed representation on a 0.13μm process by comparing the performance sensitivity deduced from this representation to sensitivity values obtained from electrical simulations performed with the full process model of the foundry
Type de document :
Communication dans un congrès
ESSCIRC'03: 29th European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal, pp.595-598, 2003
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00239459
Contributeur : Nadine Azemard <>
Soumis le : mardi 5 février 2008 - 18:02:54
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18

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  • HAL Id : lirmm-00239459, version 1

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Benoit Lasbouygues, J. Schindler, S. Engels, Philippe Maurine, Xavier Michel, et al.. Continuous Representation of the Performance of a CMOS Library. ESSCIRC'03: 29th European Solid-State Circuits Conference, Sep 2003, Estoril, Portugal, pp.595-598, 2003. 〈lirmm-00239459〉

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