Skip to Main content Skip to Navigation
Conference papers

Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology

Régis Roubadia 1 Sami Ajram 1 Guy Cathébras 2
1 ATMEL [Rousset]
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.
Keywords : CMOS Integrated Circuits Phase Locked Loops Voltage-Controlled Oscillators Multiphase Direct Realignment Multiphase Realigned PLL Phase Locked Loop Standard CMOS Process Submicronic CMOS Technology Voltage Controlled Oscillator
Document type :
Conference papers
Complete list of metadata
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00265700
Contributor : Guy Cathébras <>
Submitted on : Wednesday, March 19, 2008 - 11:01:56 PM
Last modification on : Thursday, May 24, 2018 - 3:59:20 PM

Identifiers

Collections

CNRS | LIRMM | MIPS | UNIV-MONTPELLIER

Citation

Régis Roubadia, Sami Ajram, Guy Cathébras. Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology. ISCAS'07: IEEE International Symposium on Circuits and Systems, May 2007, New Orleans, LA, USA, pp.2490-2493, ⟨10.1109/ISCAS.2007.378744⟩. ⟨lirmm-00265700⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

108