Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology

Abstract : This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.
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Communication dans un congrès
ISCAS'07: IEEE International Symposium on Circuits and Systems, May 2007, New Orleans, LA, USA, pp.2490-2493, 2007, 〈http://www.iscas2007.org/〉. 〈10.1109/ISCAS.2007.378744〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00265700
Contributeur : Guy Cathébras <>
Soumis le : mercredi 19 mars 2008 - 23:01:56
Dernière modification le : jeudi 11 janvier 2018 - 06:14:31

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Régis Roubadia, Sami Ajram, Guy Cathébras. Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology. ISCAS'07: IEEE International Symposium on Circuits and Systems, May 2007, New Orleans, LA, USA, pp.2490-2493, 2007, 〈http://www.iscas2007.org/〉. 〈10.1109/ISCAS.2007.378744〉. 〈lirmm-00265700〉

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