Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2007

Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology

Régis Roubadia
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  • PersonId : 836160
Sami Ajram
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  • PersonId : 836161

Abstract

This paper presents a novel PLL and VCO concept based on the multi-phase direct realignment. A multiphase realigned VCO and PLL operating in the 80-240 MHz frequency range have been realized in 0.18mum standard CMOS process, with a 1.8 V power supply voltage. A comparison between realigned and not realigned PLLs showed a jitter improvement by a factor 2 at 240 MHz without increasing the power consumption, which is 2.4 mW at 240 MHz.
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Dates and versions

lirmm-00265700 , version 1 (19-03-2008)

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Régis Roubadia, Sami Ajram, Guy Cathébras. Design of a Low Jitter Multi-Phase Realigned PLL in Submicronic CMOS Technology. ISCAS'07: IEEE International Symposium on Circuits and Systems, May 2007, New Orleans, LA, USA, pp.2490-2493, ⟨10.1109/ISCAS.2007.378744⟩. ⟨lirmm-00265700⟩
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