Power Driven Chaining of Flip-Flops in Scan Architectures - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2002

Power Driven Chaining of Flip-Flops in Scan Architectures

Abstract

Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.
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lirmm-00268492 , version 1 (01-04-2008)

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Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Power Driven Chaining of Flip-Flops in Scan Architectures. ITC: International Test Conference, Oct 2002, Baltimore, United States. pp.796-803, ⟨10.1109/TEST.2002.1041833⟩. ⟨lirmm-00268492⟩
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