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Integration of Robustness in the Design of a Cell

Abstract : When exposed to an harsh environment in space, high atmosphere or even on earth, Integrated Circuits undergo soft errors. Among these events the most worrying is an electrical upset, so called Single Event Upset (SEU) evidenced in latches. We present here the circuit architecture of a new SEU hardened latch. The hardening is based on an integrated redundancy of the information and a high impedance state switching. The design prevents perturbation to propagate inside the latch and saves an uncorrupted information source for recovery mechanisms. Post layout circuit simulations are used to verify the hardness assurance of this design; we also compare it to usual techniques and report significant improvements for its use in SoC.
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Jean-Max Dutertre, Fernand-Michel Roche, Guy Cathébras. Integration of Robustness in the Design of a Cell. SoC Design Methodologies - International Conference on Very Large Scale Integration of Systems-on-Chip, 2002, Montpellier, France. pp.229-239, ⟨10.1007/978-0-387-35597-9_20⟩. ⟨lirmm-00268502⟩



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