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Conference papers

Low Voltage Testing of Gate Oxide Short in CMOS Technology

Michel Renovell 1 Jean-Marc J.-M. Galliere 2 Florence Azaïs 1 yves Bertrand 1 
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
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Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00268526
Contributor : Christine Carvalho De Matos Connect in order to contact the contributor
Submitted on : Tuesday, April 1, 2008 - 9:27:39 AM
Last modification on : Friday, October 22, 2021 - 3:07:37 PM

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  • HAL Id : lirmm-00268526, version 1

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

Citation

Michel Renovell, Jean-Marc J.-M. Galliere, Florence Azaïs, yves Bertrand. Low Voltage Testing of Gate Oxide Short in CMOS Technology. DDECS: Design and Diagnostics of Electronic Circuits and Systems, 2002, Brno, Czech Republic. pp.168-174. ⟨lirmm-00268526⟩

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