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Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application

Abstract : New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00268531
Contributor : Christine Carvalho de Matos <>
Submitted on : Tuesday, April 1, 2008 - 9:27:41 AM
Last modification on : Tuesday, June 26, 2018 - 1:18:33 AM

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Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, C. Diou, et al.. Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.553-566, ⟨10.1109/DATE.2002.998355⟩. ⟨lirmm-00268531⟩

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