Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2002

Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application

Abstract

New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures.
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Dates and versions

lirmm-00268531 , version 1 (01-04-2008)

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Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, C. Diou, et al.. Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. pp.553-566, ⟨10.1109/DATE.2002.998355⟩. ⟨lirmm-00268531⟩
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