Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application

Abstract : New parallel execution based machine paradigms must be considered. Thanks to their high level of flexibility structurally programmable architectures are potentially interesting candidates to overcome classical CPUs limitations. Based on a parallel execution model, we present in this paper a new dynamically reconfigurable architecture, dedicated to data oriented applications acceleration. Principles, realizations and comparative results will be exposed for some classical applications, targeted on different architectures.
Type de document :
Communication dans un congrès
DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, pp.553-566, 2002, 〈10.1109/DATE.2002.998355〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00268531
Contributeur : Christine Carvalho de Matos <>
Soumis le : mardi 1 avril 2008 - 09:27:41
Dernière modification le : mardi 26 juin 2018 - 01:18:33

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Gilles Sassatelli, Lionel Torres, Pascal Benoit, Thierry Gil, C. Diou, et al.. Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Application. DATE: Design, Automation and Test in Europe, Mar 2002, Paris, France. Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, pp.553-566, 2002, 〈10.1109/DATE.2002.998355〉. 〈lirmm-00268531〉

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