With the reduction of distances between wires in deep sub-micron technologies, coupling capacitances are becoming significant. This increase of capacity causes noise capable of propagating a logical fault. A poor evaluation of the crosstalk could be at the root of a malfunction of the circuit. Closed-form formulas are particularly efficient at determining design rules. From an analytical expression for crosstalk evaluation, we explore the performance gain through different intra-layer dielectrics, for a given typical geometry of an upper metal level of a deep sub-micron technology. This model predicts that by using a low-k dielectric equal to two, one can reduce the crosstalk voltage by about 25%, which can be employed on a possible reduction of the space between lines.