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A Simple and Effective Compression Scheme for Test Pins Reduction

Abstract : We present a simple and effective method for test pin reduction. It must be noticed first that this method is particularly well adapted to the test of SoC since it only deals with test data and does not require any knowledge of the embedded cores. Secondly, it does not induce any delay penalty neither in the circuit itself nor during decompression.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269326
Contributor : Christine Carvalho de Matos <>
Submitted on : Wednesday, April 2, 2008 - 4:46:00 PM
Last modification on : Thursday, December 17, 2020 - 9:35:05 AM

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Marie-Lise Flottes, Régis Poirier, Bruno Rouzeyre. A Simple and Effective Compression Scheme for Test Pins Reduction. 7th IEEE International Workshop on High Level Design Validation and Test (HLDVT), Oct 2002, Cannes, France. pp.165-168, ⟨10.1109/HLDVT.2002.1224447⟩. ⟨lirmm-00269326⟩

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