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Scan Cell Ordering for Low Power Scan Testing

Yves Bonhomme 1 Patrick Girard 1 Christian Landrault 1 Serge Pravossoudovitch 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two steps heuristic procedure that can be exploited by any chip layout program before flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 34% and 18% respectively for experimented ISCAS benchmark circuits.
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Contributor : Christine Carvalho de Matos <>
Submitted on : Saturday, January 21, 2017 - 1:08:35 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM
Long-term archiving on: : Saturday, April 22, 2017 - 12:50:13 PM


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  • HAL Id : lirmm-00269337, version 1



Yves Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Scan Cell Ordering for Low Power Scan Testing. ETW: European Test Workshop, May 2002, Corfu, Greece. ⟨lirmm-00269337⟩



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