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A Unified DFT Approach for BIST and External Test

Marie-Lise Flottes 1 Christian Landrault 1 Aurélia Petitqueux 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269517
Contributor : Christine Carvalho de Matos <>
Submitted on : Thursday, April 3, 2008 - 8:21:40 AM
Last modification on : Thursday, December 17, 2020 - 9:37:25 AM

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Marie-Lise Flottes, Christian Landrault, Aurélia Petitqueux. A Unified DFT Approach for BIST and External Test. Journal of Electronic Testing, Springer Verlag, 2003, 19 (1), pp.49-60. ⟨10.1023/A:1021943912494⟩. ⟨lirmm-00269517⟩

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