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Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 2003

A Unified DFT Approach for BIST and External Test

Abstract

This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.

Dates and versions

lirmm-00269517 , version 1 (03-04-2008)

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Marie-Lise Flottes, Christian Landrault, Aurélia Petitqueux. A Unified DFT Approach for BIST and External Test. Journal of Electronic Testing: : Theory and Applications, 2003, 19 (1), pp.49-60. ⟨10.1023/A:1021943912494⟩. ⟨lirmm-00269517⟩
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