Defect-Oriented Dynamic Fault Models for Embedded-SRAMs

Abstract : This paper presents the results of resistive fault insertion in the core-cell array and in the address decoder of the infineon 0.13µm embbeded-SRAM family. Resistive opens defects were the primary target of this study because of their growing importance in VDSMtechnologies. Electrical simulations have been performed to evaluate the effects of resistive opens in terms of functional faults detected and verify the presence of timing-dependent faults. Read disturb, deceptive read disturb and dynamic read disturb faults have beenreproduced and accurately characterized. The dependence of the fault detection on memory operating conditions, injected resistance value and clock speed have been investigated and the importance of speed testing for dynamic fault models is emphasized. Finally resistiveAddress Decoder Open Faults (ADOF) have been simulated and the conditions for maximum fault detection are discussed as well as the resulting implications for memory test.
Type de document :
Communication dans un congrès
ETW: European Test Workshop, May 2003, Maastricht, Netherlands. 8th IEEE European Test Workshop, pp.23-28, 2003
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269526
Contributeur : Christine Carvalho de Matos <>
Soumis le : jeudi 3 avril 2008 - 08:21:42
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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  • HAL Id : lirmm-00269526, version 1

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Simone Borri, Magali Hage-Hassan, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. Defect-Oriented Dynamic Fault Models for Embedded-SRAMs. ETW: European Test Workshop, May 2003, Maastricht, Netherlands. 8th IEEE European Test Workshop, pp.23-28, 2003. 〈lirmm-00269526〉

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