Defect Analysis for Delay-Fault BIST in FPGAs

Abstract : Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of look-up tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This significant result questions the use of the basic assumption - the propagation delay of a LUT is independent of the function realized by it $considered in a number of recent papers. We next demonstrate that i) some physical defects in a LUT can change its propagation delay and ii) the delay due to a timing defect within the LUT varies depending on the location of the defect. We therefore conclude that unlike what is often done in existing FPGA BIST techniques, LUTs cannot be considered as programmable black boxes during test and testing their structure, either fully or partially, is needed to guarantee complete coverage of delay faults in the FPGA.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00269553
Contributor : Christine Carvalho de Matos <>
Submitted on : Thursday, April 3, 2008 - 8:21:48 AM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS: International On-Line Testing Symposium, Jul 2003, Kos, Greece. pp.124-128, ⟨10.1109/OLT.2003.1214378⟩. ⟨lirmm-00269553⟩

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