Electrical Modeling of LSCRs in Deep Submicron CMOS Technologies for Circuit-Level Simulation of ESD - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2003

Electrical Modeling of LSCRs in Deep Submicron CMOS Technologies for Circuit-Level Simulation of ESD

Abstract

This paper presents an electrical model of a parasitic LSCR that represents the inner currents before and after triggering. It relies on the standard LSCR model before triggering, and on a PiN diode model for the post-triggering behaviour. As an illustration, the model has been validated against silicon in both 0.18/spl mu/m and 0.13/spl mu/m technologies.
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Dates and versions

lirmm-00269608 , version 1 (03-04-2008)

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Benjamin Caillard, Florence Azaïs, Pascal Nouet, Stéphanie Dournelle, Pascal Salomé. Electrical Modeling of LSCRs in Deep Submicron CMOS Technologies for Circuit-Level Simulation of ESD. BCTM 2003 - Bipolar/BiCMOS Circuits and Technology Meeting, Sep 2003, Toulouse, France. pp.97-100, ⟨10.1109/BIPOL.2003.1274943⟩. ⟨lirmm-00269608⟩
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