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Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier

Abstract : This article aims at highlighting new design issues coming from the increasing sensitivity of digital circuits towards process variability. CAD tools and current design methodologies are not anymore efficient to tackle such aspects. In particular variability is increasing the difficulty to identify setup and hold time violations. This paper is a study of failure probabilities considering device process variations on several long and short paths extracted from a RTL MAC Multiplier-Accumulator physical synthesis. This study is based on a Statistical Static Timing Analysis method, used on combinatory cells, mixed with Monte Carlo Analysis applied on sequential cells. This allows the manipulation of probability distribution functions and thus, to keep all the variability information. Setup time, hold time, and delay propagation variation figures are extracted thanks to this methodology. Several results on combinatory paths and flip-flop cells are given to underline the variability impacts.
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Contributor : Martine Peridier <>
Submitted on : Monday, May 19, 2008 - 6:03:32 PM
Last modification on : Thursday, June 11, 2020 - 5:04:05 PM




Bettina Rebaud, Marc Belleville, Christian Bernard, Zeqin Wu, Michel Robert, et al.. Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI: International Symposium on Very Large Scale Integration, Apr 2008, Montpellier, France. pp.316-321, ⟨10.1109/ISVLSI.2008.70⟩. ⟨lirmm-00280809⟩



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