An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions contain IP-Cores for BIST, which allows a reuse of the BIST hardware without modifications, but also prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced. The modularity of the test is achieved with only small modifications in the BIST control and supports a more efficient interleaving of test and repair.