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Modularer Selbsttest und Optimierte Reparaturanalyse für Eingebettete Speicher

Philipp Öhler 1 Sybille Hellebrand 1 Alberto Bosio 2 Giorgio Di Natale 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions contain IP-Cores for BIST, which allows a reuse of the BIST hardware without modifications, but also prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced. The modularity of the test is achieved with only small modifications in the BIST control and supports a more efficient interleaving of test and repair.
keyword : BIST BISR RAM
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Contributor : Giorgio Di Natale <>
Submitted on : Tuesday, October 21, 2008 - 11:07:16 AM
Last modification on : Tuesday, September 1, 2020 - 11:32:02 AM


  • HAL Id : lirmm-00332558, version 1



Philipp Öhler, Sybille Hellebrand, Alberto Bosio, Giorgio Di Natale. Modularer Selbsttest und Optimierte Reparaturanalyse für Eingebettete Speicher. ZUE'08: Zuverlässigkeit und Entwurf, Germany. pp.049-056. ⟨lirmm-00332558⟩



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