Abstract : Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.
Type de document :
Poster
ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.7, 2008
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00341799
Contributeur : Arnaud Virazel
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Soumis le : mercredi 26 novembre 2008 - 09:34:34
Dernière modification le : vendredi 2 mars 2018 - 19:36:02
Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. SoC Yield Improvement: Redundant Architectures to the Rescue. ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.7, 2008. 〈lirmm-00341799〉
