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Poster communications

SoC Yield Improvement: Redundant Architectures to the Rescue

Abstract : Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.
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Poster communications
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Contributor : Arnaud Virazel <>
Submitted on : Wednesday, November 26, 2008 - 9:34:34 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM


  • HAL Id : lirmm-00341799, version 1



Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, et al.. SoC Yield Improvement: Redundant Architectures to the Rescue. ITC'2008: International Test Conference, Oct 2008, Santa Clara, CA, United States. IEEE, pp.7, 2008. ⟨lirmm-00341799⟩



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