A Scan-BIST Structure to Test Delay Faults in Sequential Circuits - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 1999

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Abstract

Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.

Dates and versions

lirmm-00345794 , version 1 (10-12-2008)

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Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. Journal of Electronic Testing: : Theory and Applications, 1999, 14 (1/2), pp.95-102. ⟨10.1023/A:1008305507376⟩. ⟨lirmm-00345794⟩
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