A Scan-BIST Structure to Test Delay Faults in Sequential Circuits

Abstract : Delay testing that requires the application of consecutive two-pattern tests is not an easy task in a scan-based environment. This paper proposes a novel approach to the delay fault testing problem in scan-based sequential circuits. This solution is based on the combination of a BIST structure with a scan-based design to apply delay test pairs to the circuit under test.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00345794
Contributor : Arnaud Virazel <>
Submitted on : Wednesday, December 10, 2008 - 9:08:14 AM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM

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  • HAL Id : lirmm-00345794, version 1

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Patrick Girard, Christian Landrault, Véronique Moreda, Serge Pravossoudovitch, Arnaud Virazel. A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. Journal of Electronic Testing, Springer Verlag, 1999, 14 (1/2), pp.95-102. ⟨lirmm-00345794⟩

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