Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Journal Articles Journal of Electronic Testing: : Theory and Applications Year : 2001

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences

Abstract

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation will be shortly discussed at the end of the paper.
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Dates and versions

lirmm-00345796 , version 1 (19-07-2019)

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Arnaud Virazel, René M. G. David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. Journal of Electronic Testing: : Theory and Applications, 2001, 17 (3/4), pp.233-241. ⟨10.1023/A:1012259227622⟩. ⟨lirmm-00345796⟩
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