RSIC Generation: A Solution for Logic BIST

Abstract : High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness of universal test sequences produced by such a generation technique in detecting stuck-at, path delay and bridging faults, we demonstrate that using RSIC generation is one of the best and most practical way to reach a high level of defect coverage during BIST of digital circuits.
Type de document :
Communication dans un congrès
IFIP VLSI-SOC'08: 11th IFIP International Conference on VLSI, pp.111-117, 2001
Liste complète des métadonnées

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00345802
Contributeur : Arnaud Virazel <>
Soumis le : mercredi 10 décembre 2008 - 09:32:19
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

Identifiants

  • HAL Id : lirmm-00345802, version 1

Collections

Citation

René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. RSIC Generation: A Solution for Logic BIST. IFIP VLSI-SOC'08: 11th IFIP International Conference on VLSI, pp.111-117, 2001. 〈lirmm-00345802〉

Partager

Métriques

Consultations de la notice

80