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Random Adjacent Sequences: An Efficient Solution for Logic BIST

Abstract : High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution. By proving the effectiveness of universal test sequences produced by such a generation technique in detecting stuck-at, path delay and bridging faults, we demonstrate that using RSIC generation is one of the best and most practical way to reach a high level of defect coverage during BIST of digital circuits.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00345802
Contributor : Arnaud Virazel <>
Submitted on : Friday, July 19, 2019 - 6:45:54 PM
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René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SoC: Very Large Scale Integration - System-on-Chip, Dec 2001, Montpellier, France. pp.413-424. ⟨lirmm-00345802⟩

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