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On-Line Instruction-Checking in Pipelined Microprocessors

Stefano Di Carlo 1 Giorgio Di Natale 2 Mariani Riccardo 3
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges. This paper proposes an instruction-checking architecture to detect erroneous instruction executions caused by both permanent and transient errors in the internal logic of a microprocessor. Monitoring the correct activation sequence of a set of predefined microprocessor control/status signals allow distinguishing between correctly and not correctly executed instructions.
Keywords : Watchdog On-Line Test
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Contributor : Giorgio Di Natale <>
Submitted on : Tuesday, February 24, 2009 - 10:56:22 AM
Last modification on : Tuesday, September 1, 2020 - 11:32:02 AM
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Stefano Di Carlo, Giorgio Di Natale, Mariani Riccardo. On-Line Instruction-Checking in Pipelined Microprocessors. ATS: Asian Test Symposium, Nov 2008, Saporro, Japan. pp.377-382, ⟨10.1109/ATS.2008.47⟩. ⟨lirmm-00363689⟩



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