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Conference Poster Year : 2008

A Modular Memory BIST for Optimized Memory Repair

Abstract

An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of test and repair and can be achieved with only small modifications in the BIST control
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Dates and versions

lirmm-00363724 , version 1 (24-02-2009)

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Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand. A Modular Memory BIST for Optimized Memory Repair. IEEE Computer Society. IOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. 14th International On-Line Testing and Robust System Design Symposium, pp.171-172, 2008, ⟨10.1109/IOLTS.2008.30⟩. ⟨lirmm-00363724⟩
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