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Poster communications

A Modular Memory BIST for Optimized Memory Repair

Philipp Öhler 1 Alberto Bosio 2 Giorgio Di Natale 2 Sybille Hellebrand 1
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Most of the existing built-in self-repair solutions reuse IP-Cores for BIST without modifications. However, this prevents an optimized test and repair interaction. In this paper, the concept of modular BIST for memories is introduced, which supports a more efficient interleaving of test and repair and can be achieved with only small modifications in the BIST control
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Poster communications
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Contributor : Giorgio Di Natale <>
Submitted on : Tuesday, February 24, 2009 - 12:08:47 PM
Last modification on : Tuesday, September 1, 2020 - 11:32:02 AM
Long-term archiving on: : Tuesday, June 8, 2010 - 10:52:15 PM


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Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand. A Modular Memory BIST for Optimized Memory Repair. IEEE Computer Society. IOLTS: International On-Line Testing Symposium, Jul 2008, Rhodes, Greece. 14th International On-Line Testing and Robust System Design Symposium, pp.171-172, 2008, ⟨10.1109/IOLTS.2008.30⟩. ⟨lirmm-00363724⟩



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