Self-Test Techniques for Crypto-Devices

Abstract : This paper describes a generic BIST strategy for devices implementing symmetric encryption algorithms. Taking advantage of the inner iterative structures of crypto-cores, test facilities are easily set-up for circular self-test of the crypto-cores, built-in pseudo-random test generation and response analysis for other cores in the host device. Main advantages of the proposed test implementation are an architecture with no visible scan chain, 100% fault coverage on crypto-cores with negligible area overhead, availability of pseudo-random test sources and very low aliasing response compaction for other cores.
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. 〈10.1109/TVLSI.2008.2010045〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00365359
Contributeur : Bruno Rouzeyre <>
Soumis le : mardi 3 mars 2009 - 11:22:39
Dernière modification le : mardi 23 octobre 2018 - 10:46:02

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Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Self-Test Techniques for Crypto-Devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. 〈10.1109/TVLSI.2008.2010045〉. 〈lirmm-00365359〉

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