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Self-Test Techniques for Crypto-Devices

Abstract : This paper describes a generic BIST strategy for devices implementing symmetric encryption algorithms. Taking advantage of the inner iterative structures of crypto-cores, test facilities are easily set-up for circular self-test of the crypto-cores, built-in pseudo-random test generation and response analysis for other cores in the host device. Main advantages of the proposed test implementation are an architecture with no visible scan chain, 100% fault coverage on crypto-cores with negligible area overhead, availability of pseudo-random test sources and very low aliasing response compaction for other cores.
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Contributor : Bruno Rouzeyre <>
Submitted on : Tuesday, March 3, 2009 - 11:22:39 AM
Last modification on : Tuesday, September 1, 2020 - 11:32:04 AM




Giorgio Di Natale, Marion Doulcier, Marie-Lise Flottes, Bruno Rouzeyre. Self-Test Techniques for Crypto-Devices. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE, 2009, 18 (2), pp.329-333. ⟨10.1109/TVLSI.2008.2010045⟩. ⟨lirmm-00365359⟩



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