Viability of a Delay Testing of Gate Oxide Short Transistors

Abstract : Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and IDDQ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive the dynamic characteristic of the GOS as a function of the GOS resistance and location.
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Article dans une revue
Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.6
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00370370
Contributeur : Jean-Marc Galliere <>
Soumis le : mardi 24 mars 2009 - 11:19:04
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18

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  • HAL Id : lirmm-00370370, version 1

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Jean-Marc Galliere, Michel Renovell, Florence Azaïs, Yves Bertrand. Viability of a Delay Testing of Gate Oxide Short Transistors. Journal of Computer Science and Technology, Iberoamerican Science & Technology Education Consortium, 2005, 20 (2), pp.6. 〈lirmm-00370370〉

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