Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow

Abstract : The increase of within-die variations and the design margin growth are creating a need for statistical design methodologies. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts that occur during production. This method is validated for 90nm and 65nm process. Finally, this statistical timing analysis is applied to evaluate, on basic ring oscillators and combinational paths, the timing margins introduced at the design level by the traditional corner based approach.
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Article dans une revue
Journal of Embedded Computing, IOS Press, 2009, 3 (3), pp.221-229
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00371162
Contributeur : Nadine Azemard <>
Soumis le : jeudi 26 mars 2009 - 16:13:57
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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  • HAL Id : lirmm-00371162, version 1

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Sylvain Engels, Robin Wilson, Nadine Azemard, Philippe Maurine, Vincent Migairou. Timing Margin Evaluation with a Simple Statistical Timing Analysis Flow. Journal of Embedded Computing, IOS Press, 2009, 3 (3), pp.221-229. 〈lirmm-00371162〉

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