Special Issue: Power and Timing Modeling, Optimization and Simulation

Nadine Azemard 1 Lars Svensson 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : PATMOS'07, the seventeenth in a series of international workshops, took place at Gothenburg, Sweden, September 3-5, 2007. Over the years, the PATMOS meeting has evolved into an important European event, where industry and academia meet to discuss power and timing aspects in modern integrated circuits and system design. The PATMOS objective is to provide a forum to discuss and investigate the emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems. The technical program focuses on timing, performance, and power consumption as well as architectural aspects with particular emphasis on modelling, design, characterisation, analysis and optimization. A selection of the papers on low power electronics presented at the PATMOS 2007 is included in this special issue of the Journal of Embedded Computing (JEC). The JEC addresses the most innovative developments in the area of embedding computing include all aspects of embedded computing systems with emphasis on algorithms, systems, models, compilers, architectures, tools, design methodologies, test and applications. The selection of the papers has been done based on the peer reviews of the PATMOS workshop, the quality of the presentations and the feedback and comments received during and following the workshop. The papers included in this special issue are extended and updated versions of the original PATMOS papers. This special issue combines a workshop focused on power and power optimization with a journal targeting the same technologies. The intention is the dissemination of the latest research results in the area of embedding computing on low power and power optimizations.
Type de document :
Ouvrage (y compris édition critique et traduction)
N. Azémard and L. Svensson. IOS Press, Journal of Embedded Computing (JEC), 3(3), pp.155-254, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00371166
Contributeur : Nadine Azemard <>
Soumis le : jeudi 26 mars 2009 - 16:20:30
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00371166, version 1

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Nadine Azemard, Lars Svensson. Special Issue: Power and Timing Modeling, Optimization and Simulation. N. Azémard and L. Svensson. IOS Press, Journal of Embedded Computing (JEC), 3(3), pp.155-254, 2009. 〈lirmm-00371166〉

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