An Innovative Timing Slack Monitor for Variation Tolerant Circuits

Abstract : To deal with variations, statistical methodologies can be completed by monitoring techniques implemented to cope with dynamic variations while keeping optimized operating points. This paper proposes a new monitoring structure, located in parallel of a pre-defined observable flip-flop. This structure, coupled with a specific detection window generation, embedded within the clock-tree, can anticipate timing violations to prevent system failures in real-time. Performances simulated in a 45 nm technology demonstrate a scalable, low power and low area cell which can be easily inserted in a standard CAD flow.
Type de document :
Communication dans un congrès
ICICDT'09: International Conference on IC Design & Technology, May 2009, Austin, Texas, USA, pp.215-218, 2009
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00371174
Contributeur : Nadine Azemard <>
Soumis le : jeudi 26 mars 2009 - 16:34:10
Dernière modification le : jeudi 11 janvier 2018 - 06:27:19

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  • HAL Id : lirmm-00371174, version 1

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Bettina Rebaud, Marc Belleville, Edith Beigne, Michel Robert, Philippe Maurine, et al.. An Innovative Timing Slack Monitor for Variation Tolerant Circuits. ICICDT'09: International Conference on IC Design & Technology, May 2009, Austin, Texas, USA, pp.215-218, 2009. 〈lirmm-00371174〉

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